EDN

Inheritance and polymorphism of SystemVerilog OOP for UVM verification

This is the second part in a series of introductory articles on SystemVerilog (SV) object oriented programming (OOP). In the first article, we covered the basics of the class data type and the history ...
EDN

Panelists debate phased implementation of SystemVerilog

SAN DIEGO, Calif. — A proposal for a phased, coordinated implementation of SystemVerilog took some heat at a Design Automation Conference panel Wednesday (June 9), as proponents squared off against ...
Design-Reuse

Verification IP Reuse For Complex Networking Asics

Maximizing verification IP reuse improves verification productivity. The International Technology Roadmap for Semiconductors (ITRS) projects that 75 percent of design/verification productivity ...
Design-Reuse

Transaction Analysis and Debug across Language Boundaries and between Abstraction Levels

Transaction analysis and debug between multiple abstraction levels is now possible with current technology. This paper will present an API and implementation for recording transactions from SystemC, C ...