EDN

Phase noise analyzers take over from scopes

Phase noise analyzers have traditionally been RF tools, but they're seeing more use in other areas when scopes and spectrum analyzers run out of steam. Unless you work in RF, you probably haven't been ...
EDN

Phase noise and jitter — a primer for digital designers

As clock speeds in communications systems push into the GHz range, phase noise and jitter — always key issues in analog designs — are becoming increasingly critical to the performance of digital chips ...
Electronic Design

Phase-Noise Modeling, Simulation, and Propagation in Phase-Locked Loops (Part 1)

Some brief theory and typical measurements of phase noise. Standard analysis of PLL phase noise used by most CAD applications. How to produce the lowest phase noise at a PLL output. A standard design ...
Electronic Design

Select The Right PLL-based Oscillator For Your Timing Application

More than 10 years ago, the frequency control industry introduced PLL-based (phase-locked loop) oscillators, an innovation that pioneered several features previously unavailable with traditional ...
Design-Reuse

Is there a "one-size fits all" SOC PLL?

A PLL (phase-locked loop) is perhaps the most widely used analog circuit in SOCs (system-on-a-chip). Almost all SOCs with a clock rate over 30MHz use a PLL for frequency synthesis. Most SOCs use more ...
Design-Reuse

Unlock and Load: Characterizing Today's PLLs

The phase-locked loop (PLL) has become one of the most versatile tools in the communication sector. PLLs are at the heart of circuits and devices ranging from clock recovery blocks in data ...
New Electronics

Engineers should take precautions when they compare additive jitter performance, based on clock buffer data sheets

A fan-out buffer is used in timing applications that require multiple copies of a clock signal to be distributed. When choosing the right fan-out buffer for a timing application, it’s usually helpful ...