CNBC

Apache Introduces PathFinder, the Industry's First Full-chip ESD Physical Integrity Solution

SAN JOSE, Calif., May 10, 2010 (BUSINESS WIRE) -- Apache Design Solutions, the technology leader in power integrity and noise closure for chip-package-systems (CPS) convergence, today announced ...
EDN

Transistor level ESD verification in large SoC designs

When it comes to large system-on-chip (SoC) designs, there is a need for a comprehensive electrostatic discharge (ESD) verification flow that can verify both topological and geometrical constructions ...
EDN

ESD Process Shrinks I/Os Along Core Path

IC cores have shrunk significantly with ever-smaller process geometries, but the I/Os have basically been stuck at the same sizes since 0.5-micron CMOS. Now with new compact electrostatic discharge ...
Electronics Weekly

New process cuts die size, I/O and ESD

New process cuts die size, I/O and ESDNews from E-InSiteSarnoff, the company that pioneered CMOS process technology, has unveiled its TakeCharge! technology for IC design, which it claims reduces die ...
Semiconductor Engineering

Verifying Your Intent

Design rule checking (DRC), layout versus schematic (LVS) and electrical rule checking (ERC) are physical verification techniques that are mandatory today to check a design and its structures before ...