EDN

Cadence SystemVerilog pledge may ease language split

SANTA CRUZ, Calif. — Fears of a Verilog language schism may ease this week as Cadence Design Systems announces that it plans to support “aspects” of Accellera's SystemVerilog 3.1 language. Cadence's ...
EDN

SystemVerilog adoption up, Cadence survey says

SANTA CRUZ, Calif. — A recent user survey shows that adoption of the SystemVerilog language is growing rapidly, according to Cadence Design Systems. Further, the survey found, over half of ...
Design-Reuse

Cadence OVM SystemVerilog Solution Enables More Thorough Verification and Reduces Costs at Mitsubishi Electric

SAN JOSE, Calif., 25 Jan 2010-- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced today that Mitsubishi Electric Corp. has adopted Cadence® ...
Design-Reuse

Cadence Extends the Open Verification Methodology Beyond SystemVerilog to Include SystemC and e Language Support

SAN JOSE, Calif. -- Feb 23, 2009 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced the release of open source libraries for e and ...
Business Wire

Cadence and Mentor Graphics Deliver Interoperability with Open SystemVerilog Verification Methodology

SAN JOSE, Calif., & WILSONVILLE, Ore.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ:CDNS), and Mentor Graphics Corp. (NASDAQ:MENT) today announced that they will standardize on a verification ...
Electronic Design

Cadence, Mentor Team To Open Up SystemVerilog Verification

When the SystemVerilog hardware description language (HDL) came onto the scene a few years ago, it promised true openness and interoperability. Here, crowed the hype, was an HDL that would enable ...
CIOL

Cadence, Mentor standardize on Open SystemVerilog

It delivers on the promise of SystemVerilog with established interoperability mechanisms for verification IP (VIP), transaction-level and RTL models, and full integration with other languages commonly ...
Electronic Design

Cadence And Mentor Develop Open-Source SystemVerilog Methodology

EDA giants Cadence Design Systems and Mentor Graphics announced that they will create and standardize on a verification methodology based on the IEEE 1800(TM)-2005 SystemVerilog standard. Using the ...
New Electronics

Cadence and Imperas support NSITEXE in development of automotive RISC V Vector processor IP

Imperas Software and Cadence Design Systems have collaborated to enable NSITEXE, part of the DENSO Corporation, to develop a RISC-V-based processor IP for functional safety and next-generation ...
Electronics Weekly

Cadence makes logic verification OVM-savvy

Cadence Design Systems has added several enhancements, including support for the OVM (open-verification methodology)—to its Incisive logic-verification-tool lineup. Traditionally, verification ...
New Electronics

Cadence unveils NVMe 1.4 Verification IP for high-performance computing

Cadence Design Systems is making available the industry’s first Verification IP (VIP) in support of the new NVM Express 1.4 (NVMe) protocol. The Cadence VIP for NVMe 1.4 is intended to enable ...